@article {Vogelstein2007,
	title = {Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses.},
	journal = {IEEE Transactions on Neural Networks},
	volume = {18},
	number = {1},
	year = {2007},
	pages = {253{\textendash}65},
	publisher = {IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS},
	abstract = {<p>A mixed-signal very large scale integration (VLSI) chip for large scale emulation of spiking neural networks is presented. The chip contains 2400 silicon neurons with fully programmable and reconfigurable synaptic connectivity. Each neuron implements a discrete-time model of a single-compartment cell. The model allows for analog membrane dynamics and an arbitrary number of synaptic connections, each with tunable conductance and reversal potential. The array of silicon neurons functions as an address-event (AE) transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven digital bus. Address encoding and conflict resolution of spiking events are implemented via a randomized arbitration scheme that ensures balanced servicing of event requests across the array. Routing of events is implemented externally using dynamically programmable random-access memory that stores a postsynaptic address, the conductance, and the reversal potential of each synaptic connection. Here, we describe the silicon neuron circuits, present experimental data characterizing the 3 mm x 3 mm chip fabricated in 0.5-microm complementary metal-oxide-semiconductor (CMOS) technology, and demonstrate its utility by configuring the hardware to emulate a model of attractor dynamics and waves of neural activity during sleep in rat hippocampus.</p>},
	issn = {10459227},
	doi = {10.1109/TNN.2006.883007},
	url = {http://www.ncbi.nlm.nih.gov/pubmed/17278476},
	author = {Vogelstein, Joshua T and Mallik, Udayan and Vogelstein, Joshua T and Cauwenberghs, Gert}
}
